{"id":63391,"date":"2025-05-20T21:32:06","date_gmt":"2025-05-20T18:02:06","guid":{"rendered":"https:\/\/afaghhosting.net\/blog\/cve-2025-37964-linux-kernel-intel-x86-tlb-flush-inadvertent-skipping-vulnerability\/"},"modified":"2025-05-20T21:32:06","modified_gmt":"2025-05-20T18:02:06","slug":"cve-2025-37964-linux-kernel-intel-x86-tlb-flush-inadvertent-skipping-vulnerability","status":"publish","type":"post","link":"https:\/\/afaghhosting.net\/blog\/cve-2025-37964-linux-kernel-intel-x86-tlb-flush-inadvertent-skipping-vulnerability\/","title":{"rendered":"CVE-2025-37964 &#8211; Linux Kernel: Intel X86 TLB Flush Inadvertent Skipping Vulnerability"},"content":{"rendered":"<p><strong>CVE ID : <\/strong>CVE-2025-37964<br \/>\n<br \/>\n<strong>Published : <\/strong> May 20, 2025, 4:15 p.m. | 54\u00a0minutes ago<br \/>\n<br \/>\n<strong>Description : <\/strong>In the Linux kernel, the following vulnerability has been resolved:<\/p>\n<p>x86\/mm: Eliminate window where TLB flushes may be inadvertently skipped<\/p>\n<p>tl;dr: There is a window in the mm switching code where the new CR3 is<br \/>\nset and the CPU should be getting TLB flushes for the new mm.  But<br \/>\nshould_flush_tlb() has a bug and suppresses the flush.  Fix it by<br \/>\nwidening the window where should_flush_tlb() sends an IPI.<\/p>\n<p>Long Version:<\/p>\n<p>=== History ===<\/p>\n<p>There were a few things leading up to this.<\/p>\n<p>First, updating mm_cpumask() was observed to be too expensive, so it was<br \/>\nmade lazier.  But being lazy caused too many unnecessary IPIs to CPUs<br \/>\ndue to the now-lazy mm_cpumask().  So code was added to cull<br \/>\nmm_cpumask() periodically[2].  But that culling was a bit too aggressive<br \/>\nand skipped sending TLB flushes to CPUs that need them.  So here we are<br \/>\nagain.<\/p>\n<p>=== Problem ===<\/p>\n<p>The too-aggressive code in should_flush_tlb() strikes in this window:<\/p>\n<p>\t\/\/ Turn on IPIs for this CPU\/mm combination, but only<br \/>\n\t\/\/ if should_flush_tlb() agrees:<br \/>\n\tcpumask_set_cpu(cpu, mm_cpumask(next));<\/p>\n<p>\tnext_tlb_gen = atomic64_read(&amp;next-&gt;context.tlb_gen);<br \/>\n\tchoose_new_asid(next, next_tlb_gen, &amp;new_asid, &amp;need_flush);<br \/>\n\tload_new_mm_cr3(need_flush);<br \/>\n\t\/\/ ^ After &#8216;need_flush&#8217; is set to false, IPIs *MUST*<br \/>\n\t\/\/ be sent to this CPU and not be ignored.<\/p>\n<p>        this_cpu_write(cpu_tlbstate.loaded_mm, next);<br \/>\n\t\/\/ ^ Not until this point does should_flush_tlb()<br \/>\n\t\/\/ become true!<\/p>\n<p>should_flush_tlb() will suppress TLB flushes between load_new_mm_cr3()<br \/>\nand writing to &#8216;loaded_mm&#8217;, which is a window where they should not be<br \/>\nsuppressed.  Whoops.<\/p>\n<p>=== Solution ===<\/p>\n<p>Thankfully, the fuzzy &#8220;just about to write CR3&#8221; window is already marked<br \/>\nwith loaded_mm==LOADED_MM_SWITCHING.  Simply checking for that state in<br \/>\nshould_flush_tlb() is sufficient to ensure that the CPU is targeted with<br \/>\nan IPI.<\/p>\n<p>This will cause more TLB flush IPIs.  But the window is relatively small<br \/>\nand I do not expect this to cause any kind of measurable performance<br \/>\nimpact.<\/p>\n<p>Update the comment where LOADED_MM_SWITCHING is written since it grew<br \/>\nyet another user.<\/p>\n<p>Peter Z also raised a concern that should_flush_tlb() might not observe<br \/>\n&#8216;loaded_mm&#8217; and &#8216;is_lazy&#8217; in the same order that switch_mm_irqs_off()<br \/>\nwrites them.  Add a barrier to ensure that they are observed in the<br \/>\norder they are written.<br \/>\n<br \/>\n<strong>Severity:<\/strong> 0.0 | NA<br \/>\n<br \/>\nVisit the link for more details, such as CVSS details, affected products, timeline, and more&#8230;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>CVE ID : CVE-2025-37964 Published : May 20, 2025, 4:15 p.m. | 54\u00a0minutes ago Description : In the Linux kernel, the following vulnerability has been resolved: x86\/mm: Eliminate window where TLB flushes may be inadvertently skipped tl;dr: There is a window in the mm switching code where the new CR3 is set and the CPU &hellip;<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[26],"tags":[],"class_list":["post-63391","post","type-post","status-publish","format-standard","hentry","category-vulnerability"],"_links":{"self":[{"href":"https:\/\/afaghhosting.net\/blog\/wp-json\/wp\/v2\/posts\/63391","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/afaghhosting.net\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/afaghhosting.net\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/afaghhosting.net\/blog\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/afaghhosting.net\/blog\/wp-json\/wp\/v2\/comments?post=63391"}],"version-history":[{"count":0,"href":"https:\/\/afaghhosting.net\/blog\/wp-json\/wp\/v2\/posts\/63391\/revisions"}],"wp:attachment":[{"href":"https:\/\/afaghhosting.net\/blog\/wp-json\/wp\/v2\/media?parent=63391"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/afaghhosting.net\/blog\/wp-json\/wp\/v2\/categories?post=63391"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/afaghhosting.net\/blog\/wp-json\/wp\/v2\/tags?post=63391"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}