{"id":81340,"date":"2026-07-01T17:02:30","date_gmt":"2026-07-01T13:32:30","guid":{"rendered":"https:\/\/afaghhosting.net\/blog\/cve-2026-53354-arm64-errata-mitigate-tlbi-errata-on-various-arm-cpus\/"},"modified":"2026-07-01T17:02:30","modified_gmt":"2026-07-01T13:32:30","slug":"cve-2026-53354-arm64-errata-mitigate-tlbi-errata-on-various-arm-cpus","status":"publish","type":"post","link":"https:\/\/afaghhosting.net\/blog\/cve-2026-53354-arm64-errata-mitigate-tlbi-errata-on-various-arm-cpus\/","title":{"rendered":"CVE-2026-53354 &#8211; arm64: errata: Mitigate TLBI errata on various Arm CPUs"},"content":{"rendered":"<p>CVE ID :CVE-2026-53354<\/p>\n<p>  Published : July 1, 2026, 1:32 p.m. | 14\u00a0minutes ago<\/p>\n<p>  Description :In the Linux kernel, the following vulnerability has been resolved:<\/p>\n<p>arm64: errata: Mitigate TLBI errata on various Arm CPUs<\/p>\n<p>A number of CPUs developed by Arm suffer from errata whereby a broadcast<br \/>\nTLBI;DSB sequence may complete before the global observation of writes<br \/>\nwhich are translated by an affected TLB entry.<\/p>\n<p>These errata ONLY affect the completion of memory accesses which have<br \/>\nbeen translated by an invalidated TLB entry, and these errata DO NOT<br \/>\naffect the actual invalidation of TLB entries. TLB entries are removed<br \/>\ncorrectly.<\/p>\n<p>This issue has been assigned CVE ID CVE-2025-10263.<\/p>\n<p>To mitigate this issue, Arm recommends that software follows any<br \/>\naffected TLBI;DSB sequence with an additional TLBI;DSB, which will<br \/>\nensure that all memory write effects affected by the first TLBI have<br \/>\nbeen globally observed. The additional TLBI can use any operation that<br \/>\nis broadcast to affected CPUs, and the additional DSB can use any option<br \/>\nthat is sufficient to complete the additional TLBI.<\/p>\n<p>The ARM64_WORKAROUND_REPEAT_TLBI workaround is sufficient to mitigate<br \/>\nthe issue. Enable this workaround for affected CPUs, and update the<br \/>\nsilicon errata documentation accordingly.<\/p>\n<p>Note that due to the manner in which Arm develops IP and tracks errata,<br \/>\nsome CPUs share a common erratum number.<\/p>\n<p>  Severity: 0.0 | NA<\/p>\n<p>  Visit the link for more details, such as CVSS details, affected products, timeline, and more&#8230;\u00a0<\/p>\n","protected":false},"excerpt":{"rendered":"<p>CVE ID :CVE-2026-53354 Published : July 1, 2026, 1:32 p.m. | 14\u00a0minutes ago Description :In the Linux kernel, the following vulnerability has been resolved: arm64: errata: Mitigate TLBI errata on various Arm CPUs A number of CPUs developed by Arm suffer from errata whereby a broadcast TLBI;DSB sequence may complete before the global observation of &hellip;<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[26],"tags":[],"class_list":["post-81340","post","type-post","status-publish","format-standard","hentry","category-vulnerability"],"_links":{"self":[{"href":"https:\/\/afaghhosting.net\/blog\/wp-json\/wp\/v2\/posts\/81340","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/afaghhosting.net\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/afaghhosting.net\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/afaghhosting.net\/blog\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/afaghhosting.net\/blog\/wp-json\/wp\/v2\/comments?post=81340"}],"version-history":[{"count":0,"href":"https:\/\/afaghhosting.net\/blog\/wp-json\/wp\/v2\/posts\/81340\/revisions"}],"wp:attachment":[{"href":"https:\/\/afaghhosting.net\/blog\/wp-json\/wp\/v2\/media?parent=81340"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/afaghhosting.net\/blog\/wp-json\/wp\/v2\/categories?post=81340"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/afaghhosting.net\/blog\/wp-json\/wp\/v2\/tags?post=81340"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}